学術論文

  • JJAP
  • IEICE
  • JSSC
  1. H. Sebe, D. Kanemoto, T. Hirose, “Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting,” IEICE Trans. Electron., vol. E107-C, no. 10, pp. , 2024. [doi]
  2. Y. Itotagawa, K. Atsumi, H. Sebe, D. Kanemoto, T. Hirose, “Programmable Differential Bandgap Reference Circuit for Ultra-Low-Power CMOS LSIs,” IEICE Trans. Electron., vol. E107-C, no. 10, pp. , 2024. [doi]
  3. S. Sumi, H. Sebe, D. Kanemoto and T. Hirose, “Sub-50-mV power supply, recursive stacking body bias NAND gate for extremely low-voltage CMOS LSI”, Jpn. J. Appl. Phys. 63 03SP87, 2024. [doi]
  4. K. Mii, D. Kanemoto, T. Hirose, ”0.36μW/channel Capacitively-coupled Chopper Instrumentation Amplifier in EEG Recording Wearable Devices for Compressed Sensing Framework,” Jpn. J. Appl. Phys. 63 03SP54, 2024. [doi]
  5. Y. Mizuno, H. Sebe, D. Kanemoto, T. Hirose, “Ultra-low power low-dropout linear regulator with a load current tracking bias current generator for loT devices,” Jpn. J. Appl. Phys. 63 02SP96 2024. [doi]
  6. K. Mii, D. Kanemoto, T. Hirose, “Low Quiescent Current LDO with FVF-Based PSRR Enhanced Circuit for EEG Recording Wearable Devices,” Jpn. J. Appl. Phys. 63 03SP33, 2024. [doi]
  7. R. Matsuzuka, S. Kanzaki, K. Matsumoto, N. Kuroki, M. Numa, D. Kanemoto, T. Hirose, “Switched-capacitor voltage buck converter with variable step-down and switching frequency controllers for low-power and high-efficiency IoT devices,” Jpn. J. Appl. Phys. 62, SC1082-1-SC1082-7, 2023. [doi]
  8. K. Matsumoto, R. Ikeda, H. Sebe, N. Kuroki, M. Numa, D. Kanemoto, T. Hirose, “Fully-integrated switched-capacitor voltage boost converter with digital maximum power point tracking for low-voltage energy harvesting”, Jpn. J. Appl. Phys. 62, SC1071-1-SC1071-9, 2023. [doi]
  9. Y. Okabe, D. Kanemoto, O. Maida, and T. Hirose, “Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series,” IEICE Trans. Fundamentals, vol. E105-A, no.10, pp.1429-1433, 2022.
  10. Y. Harada, D. Kanemoto, T. Inoue, O. Maida and T. Hirose, “Image quality improvement for capsule endoscopy based on compressed sensing with K-SVD dictionary learning,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E105-A, no. 4, pp. 743-747, 2022. [doi]
  11. O. Maida, D. Kanemoto and T. Hirose, ”Characterization of deep interface states in SiO2/B-doped diamond using the transient photocapacitance method,” Thin solid films, vol. 741, 139026, 2021. [doi]
  12. K. Urazoe, N. Kuroki, A. Maenaka, H. Tsutsumi, M. Iwabuchi, K. Fuchuya, T. Hirose, and M. Numa, “Automated fish bone detection in X-ray images with convolutional neural network and synthetic image generation,” IEEJ Transactions on Electrical and Electronic Engineering, vol. 16, no. 11, pp. 1510-1517, 2021. [doi]
  13. H. Sebe, K. Matsumoto, R. Matsuzuka, O. Maida, D. Kanemoto, and T. Hirose, “A self-bias NAND gate and its application to non-overlapping clock generator for extremely low-voltage CMOS LSIs,” Jpn. J. Appl. Phys. 60, SBBL06, 2021. [doi]
  14. M. Nishi, K. Matsumoto, N. Kuroki, M. Numa, H. Sebe, R. Matsuzuka, O. Maida, D. Kanemoto, and T. Hirose, “A 35-mV supply ring oscillator consisting of stacked body bias Inverters for extremely low-voltage LSIs,” IEICE Electron. Express, vol. 18, issue 6, 20210065, 2021. [doi]
  15. K. Urazoe, N. Kuroki, Y. Kato, S. Ohtani, T. Hirose, and M. Numa, “Multi-category image super-resolution with convolutional neural network and multi-task learning,” IEICE Transactions on Information and Systems, vol. E104-D, no. 1, pp. 183-193, 2021. [doi]
  16. K. Urazoe, N. Kuroki, T. Hirose, and M. Numa, “Combination of convolutional neural network architecture and its learning method for rotation-invariant handwritten digit recognition,” IEEJ Transactions on Electrical and Electronic Engineering, vol. 16, no. 1, pp. 161-163, 2021. [doi]
  17. M. Chung, T. Hirose, T. Ono, and P. Chen, “A 115x Conversion-Ratio Thermoelectric Energy-Harvesting Battery Charger for the Internet of Things,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, issue 11, pp. 4110-4121, 2020. [doi]
  18. T. Hirose and Y. Nakazawa, “Design of switched-capacitor voltage boost converter for low-voltage and low-power energy harvesting systems,” IEICE Trans. Electron., vol. E103-C, no. 10, pp. 446-457, 2020. [doi]
  19. K. Urazoe, N. Kuroki, Y. Kato, S. Ohtani, T. Hirose, and M. Numa, “Improvement of Luminance Isotropy for Convolutional Neural Networks-based Image Super-Resolution,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E103-A, no. 7, pp. 955-958, 2020. [doi]
  20. K. Matsumoto, H. Asano, Y. Nakazawa, N. Kuroki, M. Numa, O. Maida, D. Kanemoto, and T. Hirose, “An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems,” IEICE Electron. Express, vol. 17, issue 11, 20200103, 2020. [doi]
  21. 浦添和哉, 黒木修隆, 加藤 裕, 大谷真也, 廣瀬哲也, 沼 昌宏, “複数の伝搬経路を持つ畳み込みニューラルワークによる超解像,” 電気学会論文誌C, Vol.140, No.6, pp. 638-650, 2020年6月. [doi]
  22. 多谷邦彦, 黒木修隆, 竹田直人, 廣瀬哲也, 沼 昌宏, “LSTMおよびU-Netを用いた時空間解析による動画改ざん領域の検出,” 電気学会論文誌C, Vol.140, No.4, pp. 476-483, 2020年4月. [doi]
  23. R. Matsuzuka, T. Terada, K. Matsumoto, M. Kitamura, and T. Hirose, “A 42-mV startup ring oscillator using gain-enhanced self-bias inverters for extremely low voltage energy harvesting,” Jpn. J. Appl. Phys. 59, SGGL01, 2020. [doi]
  24. H. Asano, T. Hirose, T. Ozaki, N. Kuroki, and M. Numa, “An area-efficient resistor-less on-chip frequency reference for ultra-low power real-time clock application,” IEEJ Trans. Electr. and Electron. Eng., vol. 13, no. 11, pp. 1633-1641, 2018. [doi]
  25. 加藤 裕, 大谷真也, 黒木修隆, 廣瀬哲也, 沼 昌宏, “水平・垂直畳み込みニューラルネットワークを用いた超解像,” 電気学会論文誌C, vol. 138, no. 7, pp. 957-963, 2018. [doi]
  26. H. Asano, T. Hirose, Y. Kojima, N. Kuroki, and M. Numa, “A fully integrated, wide load range, high power conversion efficiency switched capacitor DC-DC converter with adaptive bias comparator for ultra-low-power power management integrated circuit,” Jpn. J. Appl. Phys. 57, 04FF03, 2018. [doi]
  27. H. Asano, T. Hirose, T. Miyoshi, K. Tsubaki, T. Ozaki, N. Kuroki, and M. Numa, “A sub-1-μs start-up time, fully-integrated 32-MHz relaxation oscillator for low-power intermittent systems,” IEICE Trans. Electron., vol. 101-C, no. 3, pp. 161-169, 2018. [doi] [KU repository]
  28. R. Matsuzuka, T. Hirose, Y. Shizuku, K. Shinonaga, N. Kuroki, and M. Numa, “An 80mV-to-1.8V conversion-range low-energy level shifter for extremely low-voltage VLSIs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, issue 8, pp. 2026-2035, 2017. [doi] [KU repository]
  29. S. Ohtani, Y. Kato, N. Kuroki, T. Hirose, and M. Numa, “Multi-channel convolutional neural networks for image super-resolution,” IEICE Trans. Informat. Syst., E100-A No.2, pp.572-580, 2017. [doi]
  30. T. Ozaki, T. Hirose, H. Asano, N. Kuroki, and M. Numa, “Ultra-low quiescent current and wide load range low-dropout linear regulator with self-biasing technique for micro-power battery management,” Jpn. J. Appl. Phys. 56, 04CF11, 2017. [doi]
  31. T. Ozaki, T. Hirose, T. Nagai, K. Tsubaki, N. Kuroki, and M. Numa, “A highly efficient switched-capacitor voltage boost converter with nano-watt MPPT controller for low-voltage energy harvesting,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E99-A, no. 12, pp. 2491-2499, 2016. [doi]
  32. T. Ozaki, T. Hirose, H. Asano, N. Kuroki, and M. Numa, “Fully-integrated high-conversion-ratio dual-output voltage boost converter with MPPT for low-voltage energy harvesting,” IEEE J. Solid-State Circuits, vol. 51, no. 10, pp. 2398-2407, 2016. [doi]
  33. Y. Kato, N. Kuroki, T. Hirose, M. Numa, “Locally weighted averaging for denoising of medical tomographic images,” Journal of Signal Processing, vol. 20, no. 4, pp. 217-220, 2016. [doi]
  34. 大谷真也, 加藤 裕, 黒木修隆, 廣瀬哲也, 沼 昌宏, “4並列の畳み込みニューラルネットワークを用いた超解像,” 電子情報通信学会論文誌 D, vol. J99-D, no. 5, pp. 588-593, 2016. [uri]
  35. Y. Kojima, T. Hirose, K. Tsubaki, T. Ozaki, H. Asano, N. Kuroki, M. Numa, “A fully on-chip 3-terminal switched capacitor DC-DC converter for low-voltage CMOS LSIs,” Jpn. J. Appl. Phys., vol. 55, No. 4S, 04EF09, 2016. [doi]
  36. Y. Shizuku, T. Hirose, N. Kuroki, M. Numa, M. Okada, “An energy-efficient 24T flip-flop consisting of standard CMOS gates for ultra-low power digital VLSIs,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E98-A, no. 12, pp. 2600-2606, 2015. [doi]
  37. K. Tsubaki, T. Hirose, N. Kuroki, and M. Numa, “A 32-kHz real-time clock oscillator with on-chip PVT variation compensation circuit for ultra-low power MCUs,” IEICE Trans. Electron., vol. 98-C, no. 5, pp. 446-453, 2015. [doi]
  38. T. Ozaki, T. Hirose, K. Tsubaki, N. Kuroki, and M. Numa, “Nano watt power rail-to-rail CMOS amplifier with adaptive biasing circuits for ultra low-power analog LSIs,” Jpn. J. Appl. Phys., vol. 54, 04DE13, 2015. [doi]
  39. Y. Shizuku, T. Hirose, N. Kuroki, M. Numa, and M. Okada, “Energy-efficient AES subbytes transformation circuit using asynchronous circuits for ultra-low voltage operation,” IEICE Electron. Express, vol. 12, no. 4, pp. 20141157, 2015. [doi]
  40. K. Tsubaki, T. Hirose, Y. Osaki, S. Shiga, N. Kuroki, and M. Numa, “A fully on-chip, 6.66-kHz, 320-nA, 56ppm/℃, CMOS relaxation oscillator with PVT variation compensation circuit,” IEICE Trans. Electron., vol. E97-C, no. 6, pp. 512-518, 2014. [doi]
  41. Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V sub-bandgap reference circuits for nano-watt CMOS LSIs,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1530-1538, 2013. [doi]
  42. I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, “A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation,” IEICE Electron. Express, vol. 10, no. 4, pp. 20130022, 2013. [doi]
  43. 橋本 明信, 中矢 知宏, 黒木 修隆, 廣瀬 哲也, 沼 昌宏, “学習型超解像のための二分木辞書,” 電子情報通信学会論文誌 D, vol. J96-D, No.2, pp. 357-361, 2013. [uri]
  44. I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, “Signal-dependent analog-to-digital conversion based on MINIMAX sampling,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E96-A, no. 2, pp. 459-468, 2013. [doi]
  45. Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “A low-power level shifter with logic error correction for extremely low-voltage digital CMOS LSIs,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1776-1783, 2012. [doi]
  46. 河嶋 和美, 中矢 知宏, 廣瀬 哲也, 黒木 修隆, 沼 昌宏, “カラー画像に対応した画質評価手法VSNRC,” 神戸大学大学院工学研究科紀要, 第3号，2011. [uri]
  47. Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “A wide input voltage range level shifter circuit for extremely low-voltage Digital LSIs,” IEICE Electron. Express, vol. 8, no. 12, pp. 890-896, 2011. [doi]
  48. K. Matsumoto, T. Hirose, Y. Osaki,　N. Kuroki, and M. Numa, “Subthreshold SRAM with write assist technique by using on-chip threshold voltage monitoring circuit,” IEICE Trans. Electron., vol. E94-C, no. 6, pp. 1042-1048, 2011. [doi]
  49. Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “Temperature-compensated nano-ampere current reference circuit with subthreshold metal-oxide-semiconductor field effect transistor resistor ladder,” Jpn. J. Appl. Phys., vol. 50, no. 4, pp. 04DE08, 2011. [doi]
  50. 河嶋 和美, 近松 慎伍, 中矢 知宏, 黒木 修隆, 廣瀬 哲也, 沼 昌宏, “クロス形状フラクタルを用いた画像の高解像度化,” 電子情報通信学会論文誌, vol. J94-D, no. 4, pp. 742-745, 2011. [uri]
  51. Y. Osaki , T. Hirose, K. Matsumoto, N. Kuroki, and M. Numa, “Robust subthreshold CMOS digital circuit design with on-chip adaptive supply voltage scaling technique,” IEICE Trans. Electron., vol. E94-C, no. 1, pp. 80-88, 2011. [doi]
  52. K. Shioki, N. Okada, K. Watanabe, T. Hirose, N. Kuroki, and M. Numa, “An error diagnosis technique based on clustering of elements,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E93-A, no. 12, pp. 2490-2496, 2010. [doi]
  53. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 1-uW, 600-ppm/℃ current reference circuit consisting of sub-threshold CMOS circuits,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 57, issue 9, pp. 681 – 685, 2010. [doi]
  54. Y. Tsugita, K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “An on-chip PVT compensation technique with current monitoring circuit for low-voltage CMOS digital LSIs,” IEICE Trans. Electron., vol. E93-C, no. 6, pp. 835-841, 2010. [doi]
  55. 上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, “サブスレッショルドMOSFETを用いたPTAT電流生成のための微小フローティング電圧源回路,” 映像情報メディア学会誌, vol. 63, no. 12, pp. 1877-1880, 2009. [doi]
  56. 次田 祐輔, 廣瀬 哲也, 上野 憲一, 浅井 哲也, 雨宮 好仁, “低電圧CMOSディジタル回路のプロセスバラツキ補正技術,” 映像情報メディア学会誌, vol. 63, no. 11, pp. 1667-1670, 2009. [doi]
  57. K. Shioki, N. Okada, T. Ishihara, T. Hirose, N. Kuroki, M. Numa, “An error diagnosis technique based on location sets to rectify subcircuits,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E92-A, no. 12, pp. 3136-3142, 2009. [doi]
  58. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “Low-voltage process-compensated VCO with on-chip process monitoring and body-biasing circuit techniques,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E92-A, pp. 3079-3081, 2009. [doi]
  59. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300-nW, 15-ppm/℃, 20-ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 44, no. 7. pp. 2047-2054, 2009. [doi]
  60. K. Seto, M. Iijima, T. Hirose, M. Numa, A. Tada, and T. Ipposhi, “Look-ahead active body-biasing scheme for SOI-SRAM with dynamic VDDM control,” IEICE Electron. Express, vol. 6, no. 8, pp. 456-460, 2009. [doi]
  61. T. Ogawa, T. Hirose, T. Asai, and Y. Amemiya, “Threshold-logic devices consisting of subthreshold CMOS circuits,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E92-A, no. 2, pp. 436-442, 2009. [doi]
  62. T. Hirose, A. Hagiwara, T. Asai, and Y. Amemiya, “A highly sensitive thermosensing CMOS circuit based on self-biasing circuit technique,” IEEJ Trans. Electr. and Electron. Eng., vol. 4, no. 2, pp. 278-286, 2009. [doi]
  63. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “Noise-induced synchronization among sub-RF CMOS analog oscillators for skew-free clock distribution,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E91-A, no. 9, pp. 2475-2481, 2008. [doi]
  64. T. Hirose, T. Asai, and Y. Amemiya, “Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs,” IEICE Electron. Express, vol. 5, no. 6, pp. 204-210, 2008. [doi]
  65. K. Yamada, T. Asai, T. Hirose, and Y. Amemiya, “On digital LSI circuits exploiting collision-based fusion gates,” Int. J. Unconv. Comput., vol. 4, no. 1, pp. 45-59, 2008. [uri]
  66. G.M. Tovar, T. Asai, T. Hirose, and Y. Amemiya, “Critical temperature sensor based on oscillatory neuron models,” Journal of Signal Processing, vol. 12, no. 1, pp. 17-24, 2008.[uri]
  67. A.K. Kikombo, T. Hirose, T. Asai, and Y. Amemiya, “Non-linear phenomena in electronic systems consisting of coupled single-electron oscillators,” Chaos, Solitons and Fractals, vol. 37, no. 1, pp. 100-107, 2008. [doi]
  68. E.S. Fukuda, G.M. Tovar, T. Asai, T. Hirose, and Y. Amemiya, “Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning,” Journal of Signal Processing, vol. 11, no. 6, pp. 439-444, 2007. [uri]
  69. K. Nakada, T. Asai, T. Hirose, H. Hayashi, and Y. Amemiya, “A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters,” Neurocomputing, vol. 71, no. 1-3, pp. 3-12, 2007. [doi]
  70. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “An inhibitory neural-network circuit exhibiting noise shaping with subthreshold MOS neuron circuits,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E90-A, no. 10, pp. 2108-2115, 2007. [doi]
  71. T. Hirose, T. Asai, and Y. Amemiya, “Pulsed neural networks consisting of single-flux-quantum spiking neurons,” Physica C, vol. 463-465, pp. 1072-1075, 2007. [doi]
  72. M. Takahashi, T. Asai, T. Hirose, and Y. Amemiya, “A CMOS reaction-diffusion device using minority-carrier diffusion in semiconductors,” International Journal of Bifurcation and Chaos, vol. 17, no. 5, pp. 1713-1719, 2007. [doi]
  73. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “CMOS smart sensor for monitoring the quality of perishables,” IEEE J. Solid-State Circuits, vol. 42, no, 4, pp. 798-803, 2007. [doi]
  74. Tovar G.M., T. Hirose, T. Asai, and Y. Amemiya, “Neuromorphic MOS circuits exhibiting precisely-timed synchronization with silicon spiking neurons and depressing synapses,” Journal of Signal Processing, vol. 10, no. 6, pp. 391-397, 2006. [uri]
  75. T. Hirose, T. Asai, and Y. Amemiya, “Power-supply circuits for ultralow-power subthreshold MOS-LSIs,” IEICE Electron. Express, vol. 3, no. 22, pp. 464-468, 2006. [doi]
  76. 萩原 淳史, 廣瀬 哲也, 浅井 哲也，雨宮 好仁, “弱反転MOSFETを用いた温度検出スイッチ回路,” 電子情報通信学会論文誌C, vol. J89-C, no. 10, pp. 654-656, 2006. [uri]
  77. T. Hirose, T. Asai, and Y. Amemiya, “Spiking neuron devices consisting of single-flux-quantum circuits,” Physica C, vol. 445-448, pp. 1020-1023, 2006. [doi]
  78. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A CMOS watchdog sensor for certifying the quality of various perishables with a wider activation energy,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E89-A, no. 4, pp. 902-907, 2006. [doi]
  79. T. Asai, T. Kamiya, T. Hirose, and Y. Amemiya, “A subthreshold analog MOS circuit for Lotka-Volterra chaotic oscillator,” Int. J. Bifurcation and Chaos, vol. 16, no. 1, pp. 207-212, 2006. [doi]
  80. T. Oya, T. Asai, R. Kagaya, T. Hirose, and Y. Amemiya, “Neuronal synchrony detection on signle-electron neural network,” Chaos, Solitons and Fractals, vol. 27, no. 4, pp. 887-894, 2006. [doi]
  81. T. Hirose, T. Matsuoka, K. Taniguchi, T. Asai, and Y. Amemiya, “Ultralow-power current reference circuit with low temperature dependence,” IEICE Trans. Electron., vol. E88-C, no. 6, pp. 1142-1147, 2005. [doi]
  82. S. Cha, T. Hirose, M. Haruoka, T. Matsuoka, and K. Taniguchi, “A CMOS IF variable gain amplifier with exponential gain control,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E88-A, no. 2, pp. 410-415, 2005. [uri]
  83. T. Asai, M. Ikebe, T. Hirose, and Y. Amemiya, “A quadrilateral-object composer for binary images with reaction-diffusion cellular automata,” Int. J. Parallel, Emergent and Distributed Systems, vol. 20, no. 1, pp. 57-68, 2005. [doi]
  84. T. Asai, Y. Kanazawa, T. Hirose, and Y. Amemiya, “Analog reaction-diffusion chip imitating the Belousov-Zhabotinsky reaction with Hardware Oregonator Model,” Int. J. Unconv. Comput., vol. 1, no. 2, pp. 123-147, 2005. [uri]
  85. M. Furuhashi, T. Hirose, H. Tsuji, M. Tachi, and K. Taniguchi, “Calculation of boron segregation at the Si(100)/SiO2 interface,” Eur. Phys. J.-Appl. Phys., vol. 27, No. 1-3, pp. 163-166, 2004. [doi]
  86. T. Hirose, R. Yoshimura, T. Ido, T. Matsuoka, and K. Taniguchi, “Watch-dog circuit for quality guarantee with subthreshold MOSFET current,” IEICE Trans. Electron., vol. E87-C, no. 11, pp. 1910-1914, 2004. [uri]
  87. M. Furuhashi, T. Hirose, H. Tsuji, M. Tachi, and K. Taniguchi, “Atomic configuration of boron pile-up at the Si/SiO2 interface,” IEICE Electron. Express, vol. 1, no. 6, pp. 126-130, 2004. [doi]
  88. Y. Matsubara, T. Asai, T. Hirose and Y. Amemiya, “Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata,” IEICE Electron. Express, vol. 1, no. 9, pp. 248-252, 2004. [doi]
  89. Y. Kanazawa, T. Asai, T. Hirose, and Y. Amemiya, “A MOS circuit for bursting neural oscillators with excitable Oregonators,” IEICE Electron. Express, vol. 1, no. 4, pp. 73-76, 2004. [doi]
  90. 多田 憲史, 廣瀬 哲也, 松岡 俊匡, 谷口 研二，前田 和宏, 酒井 保, 久保田 靖, 今井 繁規, “ポリSi TFTの過渡特性における自己発熱及びキンク効果の影響の分離評価,” 電子情報通信学会論文誌C, vol. 187-C, no. 1, pp. 186-187, 2004. [uri]
  91. 吉村 隆治, 廣瀬 哲也, 井戸 徹, 松岡 俊匡, 谷口 研二, “高精度品質保証期限モニタ回路,” 電子情報通信学会論文誌C, vol. J86-C, no. 9, pp. 1041-1043, 2003. [uri]
  92. T. Hirose, T. Shano, R. Kim, H. Tsuji, Y. Kamakura, and K. Taniguchi, “Atomic configuration study of implanted F in Si based on experimental evidence and ab initio calculations,” Mater. Sci. Eng. B, vol. 91/92, no. 30, pp. 148-151, 2002. [doi]
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