国際会議

1. R. Matsubara, D. Kanemoto, and T. Hirose, “Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing,” in Proc.　International Symposium on Circuits and Systems (ISCAS) 2024, May 19 – 22,　Sentosa Gateway, Sentosa Island, Singapore, 2024.
2. T. Miyata, D. Kanemoto, and T. Hirose，”Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements,” in Proc. IEEE Int. Conf. Consum. Electron. (ICCE), pp.1-4, Jan. 2024.
3. R. Tsunaga, D. Kanemoto, and T. Hirose，”Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing,” in Proc. IEEE Int. Conf. Consum. Electron. (ICCE), pp.1-5, Jan. 2024.
4. K. Mii, D. Kanemoto, and T. Hirose, “Low Quiescent Current LDO with FVF-Based PSRR Enhanced Circuit for EEG Recording Wearable Devices,” in Ext. Abstr. Solid State Devices and Materials (SSDM), J-3-04, p. 411, Sep. 2023.
5. Y. Mizuno, H. Sebe, D. Kanemoto, and T. Hirose, “An Ultra-Low Power Low-Dropout Regulator with a Load Current Tracking Bias Current Generator,” in Ext. Abstr. Solid State Devices and Materials (SSDM), PS-12-03, p. 911, Sep. 2023.
6. S. Sumi, H. Sebe, D. Kanemoto, and T. Hirose, “A sub-50-mV supply, recursive stacking body bias NAND gate for extremely low-voltage energy harvesting,” in Ext. Abstr. Solid State Devices and Materials (SSDM), PS-12-04, p. 913, Sep. 2023.
7. K. Mii, D. Kanemoto, and T. Hirose, “Low Quiescent Current Capacitively-coupled Chopper Instrumentation Amplifier in EEG Recording Wearable Devices for Compressed Sensing Framework,” in Ext. Abstr. Solid State Devices and Materials (SSDM), PS-12-06, p. 917, Sep. 2023.
8. H. Sebe, T. Okumura, S. Sumi, D. Kanemoto, P. -H. Chen, T. Hirose, “Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting,” Proceedings of the 49th European Solid-State Circuits Conference (ESSCIRC), pp. 325-328, Lisbon, Portugal, Sep. 11-14, 2023. [doi]
9. T. Miyata, D. Kanemoto, T. Hirose, “Random Undersampling Wireless EEG Measurement Device Using a Small Teg,” in Proc. International Symposium on Circuits and Systems (ISCAS) 2023, May 21 – 25, Monterey, California, USA, 2023. [doi]
10. Y. Itotagawa, K. Atsumi, H. Sebe, D. Kanemoto, T. Hirose, “A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices,” in Proc. International Symposium on Circuits and Systems (ISCAS) 2023, May 21 – 25, Monterey, California, USA, 2023. [doi]
11. D. Kanemoto, T. Hirose, “EEG Measurements with Compressed Sensing Utilizing EEG Signals As the Basis Matrix,” in Proc. International Symposium on Circuits and Systems (ISCAS) 2023, May 21 – 25, Monterey, California, USA, 2023. [doi]
12. N. Miura, K. Naruse, J. Shiomi, Y. Midoh, T. Hirose, T. Okidono, T. Miki, and M. Nagata, “A Triturated Sensing System,” International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 216-217, Feb. 2023. [doi]
13. R. Matsuzuka, S. Kanzaki, K. Matsumoto, N. Kuroki, M. Numa, D. Kanemoto, T. Hirose, “Fully Integrated Switched-Capacitor Buck Converter with Variable Ratio and Frequency Controllers for Ultra-Low Power LSI Systems,” Extended abstract of the 2022 International Conference on Solid State Devices and Materials (SSDM 2022), K-9-06, pp. 798-799, Sep. 26-29, 2022.
14. K. Matsumoto, R. Ikeda, H. Sebe, N. Kuroki, M. Numa, D. Kanemoto, T. Hirose, “Switched-Capacitor Voltage Boost Converter with Digital Maximum Power Point Tracking for Low-Voltage Energy Harvesting,” Extended abstract of the 2022 International Conference on Solid State Devices and Materials (SSDM 2022), K-9-07, pp. 800-801, Sep. 26-29, 2022.
15. H. Sebe, D. Kanemoto and T. Hirose, “Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting,” Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS 2022), pp. 2773-2777, Austin, USA, May 28- Jun 1, 2022. [doi]
16. H. Sebe, K. Matsumoto, R. Matsuzuka, O. Maida, D. Kanemoto and T. Hirose, “A Self-Bias NAND Gate and its Application to Non-Overlapping Clock Generator for Extremely Low-Voltage CMOS LSIs,” Extended abstract of the 2020 International Conference on Solid State Devices and Materials (SSDM 2020), A-7-02, pp. 65-66, Sep. 30, 2020.
17. M. Nishi, K. Matsumoto, N. Kuroki, M. Numa, H. Sebe, R. Matsuzuka, O. Maida, D. Kanemoto and T. Hirose, “A 34-mV startup ring oscillator using stacked body bias inverters for extremely low-voltage thermoelectric energy harvesting,” Proceedings of the 18th IEEE international new circuits and systems conference (NEWCAS 2020), pp. 38-41, Jun. 16-19, 2020. [doi]
18. K. Taya, N. Kuroki, N. Takeda, T. Hirose and M. Numa, “Detecting tampered regions in JPEG images via CNN,” Proceedings of the 18th IEEE international new circuits and systems conference (NEWCAS 2020), pp. 202-205, Jun. 16-19, 2020. [doi]
19. T. Haraguchi, N. Kuroki, T. Hirose and M. Numa, “CNN-based segmentation and recognition of traffic signs with parameter regions,” Proceedings of 2020 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2020), pp.377-380, Hawaii, USA, Feb. 28-Mar. 2, 2020.
20. K. Urazoe, N. Kuroki, T. Hirose and M. Numa, “Rotation invariant-digits recognition with single convolutional neural networks,” Proceedings of 2020 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2020), pp.618-621, Hawaii, USA, Feb. 28-Mar. 2, 2020.
21. M. Nishi, Y. Nakazawa, K. Matsumoto, N. Kuroki, M. Numa, R. Matsuzuka, O. Maida, D. Kanemoto, T. Hirose, “Sub-0.1V input, low-voltage CMOS driver circuit for multi-stage switched capacitor voltage boost converter,” Proceedings of the IEEE International Conference on Electronics Circuits and Systems, pp. 530-533, Genova, Italy, Nov. 27-29, 2019. [doi]
22. Y. Yano, S. Yoshida, S. Izumi, H. Kawaguchi, T. Hirose, M. Miyahara, T. Someya, K. Okada, I. Akita, Y. Kurui, H. Tomizawa, M. Yoshimoto, “An IoT sensor node SoC with dynamic power scheduling for sustainable operation in energy harvesting environment,” Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2019 (A-SSCC 2019), pp. 267-270, Macao, China, Nov. 4-6, 2019. [doi]
23. K. Suzuki, K. Mori, N. Kuroki, T. Hirose, and M. Numa, “A 4ch CNN hardware architecture for image super-resolution,” The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), pp. 46-50, Oct. 2019.
24. J. Akashi, S. Hojo, N. Kuroki, T. Hirose, and M. Numa, “A global placement method for RECON spare cells in ECO-friendly design style,” The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), pp. 158-163, Oct. 2019.
25. S. Ohmura, H. Nakano, N. Kuroki, T. Hirose, and M. Numa, “Incremental approaches for locating design errors: averaging epi-groups and generating additional input patterns,” The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), pp. 244-249, Oct. 2019.
26. H. Nakano, S. Ohmura, N. Kuroki, T. Hirose, and M. Numa, “An error diagnosis technique using ZDD to extract error location sets,” The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), pp. 262-267, Oct. 2019.
27. R. Matsuzuka, T. Terada, K. Matsumoto, M. Kitamura, T. Hirose, “A 42-mV startup ring oscillator using self-bias inverters for extremely low voltage energy harvesting,” Extended abstract of the 2019 International Conference on Solid State Devices and Materials (SSDM 2019), M-5-03, Sep. 5, 2019.
28. S. Kanzaki, T. Hirose, H. Asano, Y. Nakazawa, N. Kuroki, M. Numa, “Switched-capacitor voltage buck converter with step-down-ratio and clock-frequency controllers for ultra-low-power IoT devices,” Proceedings of the IEEE International Conference on Electronics Circuits and Systems, Bordeaux, France, pp. 209-212, Dec. 9-12, 2018.[doi]
29. K. Matsumoto, T. Hirose, H. Asano, Y. Tsuji, Y. Nakazawa, N. Kuroki, and M. Numa, “An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems,” Proceedings of the 2018 IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 196-200, Verona, Italy, Oct. 8-10, 2018. [doi]
30. Y. Nakazawa, T. Hirose, T. Ozaki, Y. Tsuji, S. Kanzaki, H. Asano, N. Kuroki, and M. Numa, “Analytical study of multi-stage switched-capacitor voltage boost converter for ultra-low voltage energy harvesting,” Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), pp. 1-5, Florence, Italy, May 27-30, 2018. [doi]
31. Y. Tsuji, T. Hirose, T. Ozaki, H. Asano, N. Kuroki, and M. Numa, “A 0.1–0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting,” Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2017), pp. 502-505, Batumi, Georgia, Dec. 5-8, 2017. [doi]
32. T. Sato, T. Hirose, H. Asano, N. Kuroki, and M. Numa, “An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting,” Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2017), pp. 498-501, Batumi, Georgia, Dec. 5-8, 2017. [doi]
33. H. Asano, T. Hirose, Y. Kojima, N. Kuroki, M. Numa, “A wide load range switched capacitor DC-DC converter with adaptive bias comparator for ultra-low-power power management integrated circuit,” Extended abstract of the 2017 International Conference on Solid State Devices and Materials (SSDM 2017), pp. 511-512, Sep. 20-22, 2017.
34. H. Asano, T. Hirose, T. Ozaki, N. Kuroki, and M. Numa, “An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications,” Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), pp. 477-480, Baltimore, MD, USA, May 28-31, 2017.[doi]
35. R. Shirai, J. Kono, T. Hirose, and M. Hashimoto, “Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node,” Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), pp. 124-127, Baltimore, MD, USA, May 28-31, 2017. [doi]
36. S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, “Impedance matching in magnetic-coupling-resonance wireless power transfer for small implantable devices,” 2017 IEEE Wireless Power Transfer Conference (WPTC) , pp. 1-4, Taipei, Taiwan, 2017. [doi]
37. H. Asano, T. Hirose, T. Miyoshi, K. Tsubaki, T. Ozaki, N. Kuroki, and M. Numa, “Sub-1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems,” The 22th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 35-36, Chiba/Tokyo, Japan, Jan. 16-19, 2017. [doi]
38. T. Ozaki, T. Hirose, H. Asano, N. Kuroki, M. Numa, “A 0.38-uW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management,” Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2016 (A-SSCC 2016), pp. 225-228, Toyama, Japan, Nov. 7-9, 2016. [doi]
39. S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, “Highly-efficient power transmitter coil design for small wireless sensor nodes,” Proc. of International Symposium on Antennas and Propagation (ISAP2016), pp. 512-513, Ginowan, Okinawa, Japan, 26 Oct., 2016.
40. Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, and M. Hashimoto, “Analytical study of rectifier circuit for wireless power transfer systems,” Proc. of International Symposium on Antennas and Propagation (ISAP2016), pp. 338-339, Ginowan, Okinawa, Japan, 26 Oct., 2016.
41. T. Ozaki, T. Hirose, H. Asano, N. Kuroki, and M. Numa, “A self-biased low-dropout linear regulator for ultra-low power battery management,” Extended abstract of the 2016 International Conference on Solid State Devices and Materials (SSDM 2016), pp. 463-464, Tsukuba, Japan, Sep. 26-29, 2016.
42. H. Asano, T. Hirose, K. Tsubaki, T. Miyoshi, T. Ozaki, N. Kuroki, M. Numa, “A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/℃, fully integrated current-mode RC oscillator for real-time clock applications with PVT stability,” Proceedings of the European Solid-State Circuits Conference (ESSCIRC), pp. 149-152, Lausanne, Switzerland, Sep. 12-15, 2016. [doi]
43. H. Asano, T. Hirose, T. Miyoshi, K. Tsubaki, T. Ozaki, N. Kuroki, M. Numa, “A fully integrated, 1-us start-up time, 32-MHz relaxation oscillator for low-power intermittent systems,” 14th IEEE International NEWCAS conference, pp. 1-4, Vancouver, Canada, Jun. 26-29, 2016. [doi]
44. Y. Kato, S. Ohtani, N. Kuroki, T. Hirose, M. Numa, “Image super-resolution with multi-channel convolutional neural networks,” 14th IEEE International NEWCAS conference, M-2, pp. 1-4, Vancouver, Canada, Jun. 26-29, 2016. [doi]
45. Y. Kato, N. Kuroki, T. Hirose, and M. Numa, “Noise reduction for medical tomographic images based on locally weighted averaging,” 2016 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2016), 9AM1-1-1, Mar. 2016.
46. H. Kobori, N. Kuroki, T. Hirose, and M. Numa, “Three dimensional NL-Means method for denoising continuous shooting photography,” 2016 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2016), 9AM1-1-2, Mar. 2016.
47. T. Sugimoto, N. Kuroki, T. Hirose, and M. Numa, “Anomalous behavior detection in videos based on deformable part models,” 2016 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2016), 8PM1-1-4, Mar. 2016.
48. R. Hanaki, N. Kuroki, T. Hirose, and M. Numa, “Crack extraction from noisy images with fractal dimension analysis,” 2016 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2016), 8PM1-1-5, Mar. 2016.
49. T. Ozaki, T. Hirose, H. Asano, N. Kuroki, M. Numa, “A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting,” Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2015 (A-SSCC 2015), pp. 297-300, Xiamen, China, Nov. 9-11, 2015. [doi]
50. Y. Kojima, T. Hirose, K. Tsubaki, T. Ozaki, H. Asano, N. Kuroki, and M. Numa, “A fully on-chip switched-capacitor DC-DC power converter with startup/fail-safe circuit,” Extended abstract of the 2015 International Conference on Solid State Devices and Materials (SSDM 2015), pp. 158-159, Sapporo, Japan, 29 Sep, 2015.
51. Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, and M. Hashimoto, “A wireless power transfer system for small-sized sensor applications,” Extended abstract of the 2015 International Conference on Solid State Devices and Materials (SSDM 2015), pp. 154-155, Sapporo, Japan, 29 Sep. 2015.
52. R. Matsuzuka, T. Hirose, Y. Shizuku, N. Kuroki, and M. Numa, “A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs,” Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2948-2951, Lisbon, Portugal, 24-27 May 2015. [doi]
53. S. Ohtani, N. Kuroki, T. Hirose, and M. Numa, “Object detection with deformable part models and deep convolutional neural networks,” Proceedings of 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2015), pp. 218-221, Mar. 2015.
54. T. Onishi, N. Kuroki, T. Hirose, and M. Numa, “Architecture of a JPEG noise reduction method with total variation,” Proceedings of 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2015), pp. 353-356, Mar. 2015.
55. K. Miyahara, N. Kuroki, T. Hirose, and M. Numa, “Bayer demosaicing with example-based super-resolution,” Proceedings of 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2015), pp. 421-424, Mar. 2015.
56. Y. Kabata, T. Hirose, N. Kuroki, and M. Numa, “An ECO-friendly design style based on reconfigurable cells, “The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), pp. 319-324, Mar. 2015.
57. T. Ozaki, T. Hirose, T. Nagai, K. Tsubaki, N. Kuroki, and M. Numa, “A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters,” The 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 1S-16, pp.30-31, Chiba/Tokyo, Japan, Jan. 19-22, 2015.
58. T. Ozaki, T. Hirose, T. Nagai, K. Tsubaki, N. Kuroki, and M. Numa, “A 0.21-V input, 73.6% efficiency, fully integrated voltage boost converter with maximum power point tracking for low-voltage energy harvesters,” Proceedings of the 40th European Solid-State Circuits Conference (ESSCIRC), pp. 255-258, Venice, Italy, Sep. 22-26, 2014.
59. T. Ozaki, T. Hirose, K. Tsubaki, N. Kuroki, and M. Numa, “A nano-watt power rail-to-rail CMOS amplifier with adaptive biasing for ultra-low power analog LSIs,” Extended abstract of the 2014 International Conference on Solid State Devices and Materials (SSDM 2014), pp. 964-965, Tsukuba, Japan, Sep. 8-11, 2014.
60. Y. Shizuku, T. Hirose, N. Kuroki, M. Numa, and M. Okada, “A 24-transistor static flip-flop consisting of NORs and inverters for low-power digital VLSIs,” 12th IEEE International NEWCAS conference, pp. 137-140, Trois-Rivieres, Canada, Jun. 22-25, 2014.
61. Y. Sugahara, K. Tsuchikawa, N. Kuroki, T. Hirose, and M. Numa, “Architecture of digital zooming function with example-based hierarchical super-resolution,” Proceedings of 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), pp. 301-304, Mar. 2014.
62. J. Oura, N. Kuroki, T. Hirose, and M. Numa, “A scene matching method for TV programs based on audio features,” Proceedings of 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), pp. 361-364, Mar. 2014.
63. N. Izumi, N. Kuroki, T. Hirose, and M. Numa, “Estimation of visual importance map for image quality assessment,” Proceedings of 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), pp. 501-504, Mar. 2014.
64. S. Ijiri, N. Kuroki, T. Hirose, and M. Numa, “Scene segmentation for TV programs based on a bag-of-visual Words model,” Proceedings of 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), pp. 41-44, Mar. 2014.
65. T. Hirose, “Design of an ultra-low power CMOS amplifier for low-voltage power-aware analog LSIs,” The IEEE 10th international Conference on ASIC (ASICON), pp. 99-102, Shenzhen, China, Oct. 28-31, 2013.
66. N. Katayama, H. Sakamoto, T. Hirose, N. Kuroki, and M. Numa, “An error diagnosis technique using QBF solver to fix LUT functions,” The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), pp. 28-33, Oct. 2013.
67. Y. Shizuku, T. Hirose, Y. Danno, N. Kuroki, and M. Numa, “A compact and energy-efficient Muller C-element for low-voltage asynchronous CMOS digital circuits,” The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), pp. 118-122, Oct. 2013.
68. K. Kugai, Y. Shizuku, T. Hirose, N. Kuroki, and M. Numa, “A technique for accelerating adaptive super resolution technique based on local features of images using GPU,” The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), pp. 170-175, Oct. 2013.
69. Y. Kabata, T. Hirose, N. Kuroki, and M. Numa, “Technology remapping based on multiple solutions for post-mask functional ECO,” The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), pp. 253-258, Oct. 2013.
70. A. Kiriyama, R. Matsuzuka, K. Michibata, T. Kitayama, Y. Shizuku, T. Hirose, N. Kuroki, and M. Numa, “A memory-saving technique for 4K super-resolution circuit with binary tree dictionary,” The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), pp. 360-365, Oct. 2013.
71. K. Tsubaki, T. Hirose, N. Kuroki, and M. Numa, “A 32.55-kHz, 472-nW, 120ppm/℃, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application,” Proceedings of the 39th European Solid-State Circuits Conference (ESSCIRC), pp. 315-318, Bucharest, Romania, Sep. 16-20, 2013.
72. K. Tsubaki, T. Hirose, Y. Osaki, S. Shiga, N. Kuroki, and M. Numa, “A 6.66-kHz, 940-nW, 56ppm/℃, fully on-chip PVT variation tolerant CMOS relaxation oscillator,” 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 97-100, Sevilla, Spain, Dec. 10-12, 2012.
73. Y. Osaki, T. Hirose, K. Tsubaki, N. Kuroki, and M. Numa, “A low-power single-slope analog-to-digital converter with digital PVT calibration,” 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 613-616, Sevilla, Spain, Dec. 10-12, 2012.
74. Y. Tsuruya, T. Hirose, Y. Osaki, N. Kuroki, M. Numa, and O. Kobayashi, “A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs,” Proceedings of the 38th European Solid-State Circuits Conference (ESSCIRC), pp. 69-72, Bordeaux, France, Sep. 17-21, 2012.
75. C. Masuda, T. Hirose, Y. Osaki, N. Kuroki, and M. Numa, “A dynamic comparator using dynamic currents of CMOS logic gates for low-power and high-efficient offset calibration,” Extended abstract of the 2012 International Conference on Solid State Devices and Materials (SSDM 2012), pp. 154-155, Kyoto, Japan, Sep. 25-27, 2012.
76. S. Shiga, T. Hirose, Y. Osaki, N. Kuroki, and M. Numa, “A delay control technique for low-voltage subthreshold CMOS digital circuits,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 555-559, Beppu, Japan, Mar. 9, 2012.
77. T. Matsuyama, H. Senzaki, K. Watanabe, T. Hirose, N. Kuroki, and M. Numa, “An error diagnosis technique based on SAT solver,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 544-548, Beppu, Japan, Mar. 9, 2012.
78. Y. Son, Y. Shizuku, T. Kogure, T. Hirose, N. Kuroki, and M. Numa, “Reduction of glitches for low-power multipliers using 4-2 compressors based on hybrid-CMOS logic style,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 534-538, Beppu, Japan, Mar. 9, 2012.
79. T. Kitayama, K. Michibata, Y. Shizuku, T. Hirose, N. Kuroki, and M. Numa, “Hardware architecture for real-time operation of learning-based super-resolution using binary search tree,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 492-496, Beppu, Japan, Mar. 9, 2012.
80. H. Senzaki, T. Matsuyama, K. Watanabe, T. Hirose, N. Kuroki, and M. Numa, “Reconfigurable cells for post-mask ECO,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 199-204, Beppu, Japan, Mar. 9, 2012.
81. Y. Shizuku, T. Kogure, T. Fujioka, T. Hirose, N. Kuroki, and M. Numa, “Saving power consumption in final stage adder of multiplier by using difference in arrival times with input signals,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 192-196, Beppu, Japan, Mar. 9, 2012.
82. J. Sasaki, Y. Shizuku, T. Hirose, N. Kuroki, and M. Numa, “A technique for accelerating SVM-based image recognition using GPU,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 28-32, Beppu, Japan, Mar. 9, 2012.
83. Hirose, Tetsuya, “Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications,” International SoC Conference 2011, pp. 24-27, Jeju, Korea, Nov. 17-18, 2011.
84. K. Isono, T. Hirose, K. Tsubaki, N. Kuroki, M. Numa, “A 18.9-nA standby current comparator with adaptive bias current generator,” Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2011, pp. 237-240, Jeju, Korea, Nov. 14-16, 2011.
85. K. Isono, T. Hirose, Y. Osaki, N. Kuroki, M. Numa, “Current compensation circuit for precise nano-ampere current reference,” Extended abstract of the 2011 International Conference on Solid State Devices and Materials, pp.176-177, Nagoya, Japan, Sep. 28-30, 2011.
86. T. Nagayama, T. Hirose, Y. Osaki, N. Kuroki, M. Numa, “A 105-nW CMOS thermal sensor for power-aware applications,” 10th IEEE Conference on Sensors, pp.1265-1268, Limerick, Ireland, Oct. 28-31, 2011.
87. Y. Osaki, T. Hirose, N. Kuroki, M. Numa, “A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs,” Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC), pp.199-202, Helsinki, Finland, Sep. 12-16, 2011.
88. C. Masuda, T. Hirose, K. Matsumoto, Y. Osaki, N. Kuroki, M. Numa, “High current efficiency sense amplifier using body-bias control for ultra-low-voltage SRAM,” 54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp., Souel, Korea, Aug. 7-10, 2011.
89. Y. Osaki, T. Hirose, N. Kuroki, M. Numa, “A level shifter circuit design by using input/output voltage monitoring technique for ultra-low voltage digital CMOS LSIs,” 9th IEEE International NEWCAS conference, pp. 201-204, Bordeaux, France, Jun. 26-29, 2011.
90. Y. Osaki, T. Hirose, N. Kuroki, M. Numa, “A 95-nA, 523ppm/℃, 0.6-uW CMOS current reference circuit with subthreshold MOS resistor ladder,” The 16th Asia and South Pacific Design Automation Conference, 1D-22, pp.113-114, Yokohama, Japan, Jan. 25-28, 2011.
91. T. Hirose, K. Ueno, N. Kuroki, M. Numa, “A CMOS bandgap and sub-bandgap voltage reference circuits for nanowatt power LSIs,” Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2010, pp. 77-80, Beijing, China, Nov. 8-10, 2010.
92. Y. Osaki, T. Hirose, N. Kuroki, M. Numa, “Temperature compensated nano-ampere CMOS current reference circuit using small offset voltage,” Extended abstract of the 2010 International Conference on Solid State Devices and Materials, pp.814-815, Tokyo, Japan, Sep. 22-24, 2010.
93. T. Hirose, Y. Osaki, N. Kuroki, M. Numa, “A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities,” Proceedings of the 36th European Solid-State Circuits Conference, pp. 114-117, Sevilla, Spain, Sep. 14-16, 2010.
94. Y. Osaki, T. Hirose, N. Kuroki, M. Numa, “Nano-ampere CMOS current reference with little temperature dependence using small offset voltage,” 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, pp. 668-671, Seattle, Aug. 1st-4th 2010.
95. K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, M. Numa, “Write-assisted subthreshold SRAM by using on-chip threshold voltage monitoring circuit,” 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, pp. 133-136, Seattle, Aug. 1st-4th 2010.
96. Hirose, Tetsuya, “Reference circuit design for nano-power subthreshold CMOS LSIs,” 2010 CMOS Emerging Technologies Workshop, (Whistler, BC, CANADA), May 2010.
97. Y. Osaki, T. Hirose, K. Matsumoto, T. Tsujikawa, K. Tsubaki, N. Kuroki, M. Numa, “An on-chip delay compensation for nano-power subthreshold CMOS digital LSIs,” Workshop on Information, Nano and Photonics Technology 2009 (WINPTech2009), P27, Dec. 2009.
98. Y. Osaki, T. Hirose, K. Matsumoto, N. Kuroki, M. Numa, “Variation tolerant subthreshold adder design for ultra-low power LSIs,” Proceedings of the 35th European Solid-State Circuits Conference, Athens, Greece, Fringe P31, Sep. 2009.
99. K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, M. Numa, “Switching-voltage detection and compensation circuits for ultra-low-voltage CMOS inverters,” 52nd. IEEE International Midwest Symposium on Circuits and Systems, pp. 483-486, Aug. 2009.
100. Y. Osaki, T. Hirose, K. Matsumoto, N. Kuroki, M. Numa, “Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs,” 52nd. IEEE International Midwest Symposium on Circuits and Systems, pp. 503-506, Aug. 2009.
101. Y. Tsugita, K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “On-chip PVT compensation techniques for low-voltage CMOS digital LSIs,” 2009 International Symposium on Circuits and Systems, Taipei, Taiwan (May 24-27, 2009).
102. K. Shioki, N. Okada, T. Ishihara, T. Hirose, N. Kuroki, M. Numa, “An error diagnosis technique based on location sets to rectify subcircuits,” 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), pp. 119-124, Mar. 2009.
103. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 7 ppm/℃ CMOS voltage reference circuit based on subthreshold MOSFETs,” The 14th Asia and South Pacific Design Automation Conference, pp. 95-96, Yokohama, Japan (Jan. 19-22, 2009).
104. K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, and M. Numa, “An on-chip threshold voltage difference monitor circuit for nano-power sub-threshold digital LSIs,” Workshop on Information, Nano, and Photonics Technology, P14, Kobe, Japan (Nov. 27-28, 2008).
105. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 46-ppm/℃ temperature and process compensated current reference with on-chip threshold voltage monitoring circuit,” Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2008, pp. 161-164, Fukuoka, Japan (Nov. 3-5, 2008).
106. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 0.3-µW, 7 ppm/℃ CMOS voltage reference circuit for on-chip process monitoring in analog circuits,” Proceedings of the 34th European Solid-State Circuits Conference, pp. 398-401, Edinburgh, U.K. (Sep. 15-19, 2008).
107. T. Ogawa, T. Hirose, T. Asai, and Y. Amemiya, “Low voltage operation of master-slave flip-flops for ultra-low power subthreshold LSIs,” The International Conference on Electrical Engineering 2008, No. O-166, Okinawa, Japan (Jul. 6-10, 2008).
108. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “Noise-induced phase synchronization between nonidentical analog CMOS oscillators,” 2008 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 160-163, Gold Coast, Australia (Mar. 6-8, 2008).
109. G.M. Tovar, Fujita D., T. Asai, T. Hirose, and Y. Amemiya, “Neuromorphic MOS circuits implementing a temporal coding neural model,” 2008 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 371-374, Gold Coast, Australia (Mar. 6-8, 2008).
110. A.K. Kikombo, T. Asai, T. Hirose, and Y. Amemiya, “Neuromorphic nano-electronic circuits performing edge enhancement with single-electron devices,” 2008 International Symposium on Global COE Program of Center for Next-Generation Information Technology based on Knowledge Discovery and Knowledge Federation, Sapporo, Japan (Jan. 22-23, 2008).
111. G.M. Tovar, Fukuda E.S., T. Asai, T. Hirose, and Y. Amemiya, “Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning,” Proceedings of the 14th International Conference on Neural Information Processing, pp. 306-315, Kitakyushu, Japan (Nov. 13-16, 2007).
112. T. Ogawa, T. Hirose, T. Asai, and Y. Amemiya, “Threshold-logic systems consisting of subthreshold CMOS circuits,” Proceedings of the 2007 IEEJ International Analog VLSI Workshop, pp. 78-83, Limerick, Ireland (Nov. 7-9, 2007).
113. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “CMOS voltage reference based on the threshold voltage of a MOSFET,” Extended abstract of the 2007 International Conference on Solid State Devices and Materials, pp. 486-487, Ibaraki, Japan (Sep. 18-21, 2007).
114. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “Noise-induced synchronization among sub-RF CMOS neural oscillators for skew-free clock distribution,” Proceedings of the 2007 International Symposium on Nonlinear Theory and its Applications, pp. 329-332, Vancouver, Canada (Sep. 16-19, 2007).
115. G.M. Tovar, Fukuda S.E., T. Asai, T. Hirose, and Y. Amemiya, “Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning,” Proceedings of the 2007 International Joint Conference on Neural Networks, pp. 897-901, Florida, USA (Aug. 12-17, 2007).
116. A.K. Kikombo, T. Hirose, T. Asai, and Y. Amemiya, “Multi-valued logic circuits consisting of single-electron devices,” Proceedings of the 2007 Silicon Nanoelectronics Workshop, pp. 81-82, Kyoto, Japan (Jun. 10-11, 2007).
117. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “Floating millivolt reference for PTAT current generation in subthreshold MOS LSIs,” Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, pp. 3748-3751, New Orleans, USA (May 27-30, 2007).
118. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “Ultralow-power smart temperature sensor consisting of subthreshold MOS circuits,” The 4th International Symposium on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Mar. 5-7, 2007).
119. A.K. Kikombo, T. Hirose, T. Asai, Y. Amemiya, “Non-linear dynamics of coupled single-electron oscillator systems,” The 4th International Symposium on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Mar. 5-7, 2007).
120. Yamada K., T. Asai, T. Hirose, and Y. Amemiya, “Scale reduction of logic circuits for low-power digital LSIs with collision-based fusion gate,” The 4th International Symposium on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Mar. 5-7, 2007).
121. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “An inhibitory neural network circuit exhibiting noise shaping with subthreshold MOS neuron circuits,” Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 165-168, Shanghai, China (Mar. 3-6, 2007).
122. G.M. Tovar, T. Asai, T. Hirose, and Y. Amemiya, “Critical temperature sensor based on spiking neuron models: experimental results with discrete MOS circuits,” Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 599-602, Shanghai, China (Mar. 3-6, 2007).
123. Fukuda S.E., T. Asai, T. Hirose, and Y. Amemiya, “A novel segmentation model for neuromorphic CMOS circuits,” Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 489-492, Shanghai, China (Mar. 3-6, 2007).
124. T. Hirose, T. Asai, Y. Amemiya, “Power supply circuits for ultralow-power subthreshold CMOS smart sensor LSIs,” Proceedings of the 2006 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 558-561, Tottori, Japan (Dec. 12-15, 2006).
125. K. Ueno, T. Hirose, T. Asai, Y. Amemiya, “Ultralow-power smart temperature sensor with subthreshold CMOS circuits,” Proceedings of the 2006 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 546-549, Tottori, Japan (Dec. 12-15, 2006).
126. A. Hagiwara, T. Hirose, T. Asai, Y. Amemiya, “Critical temperature switch: a highly sensitive thermosensing device consisting of subthreshold MOSFET circuits,” Proceedings of the 2006 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 111-114, Tottori, Japan (Dec. 12-15, 2006).
127. T. Hirose, T. Asai, and Y. Amemiya, “Pulsed neural networks consisting of single-flux-quantum spiking neurons,” Program and Abstracts of the 19th International Symposium on Superconductivity, p. 329, Nagoya, Japan (Oct. 30 – Nov. 1, 2006).
128. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “Noise shaping pulse-density modulation in inhibitory neural networks with noise-sensitive subthreshold neuron circuits,” Abstracts of the 3rd International Conference of Brain-inspired Information Technology, p. 42, Kitakyushu, Japan (Sep. 27-29, 2006).
129. G.M. Tovar, T. Hirose, T. Asai, and Y. Amemiya, “Critical temperature sensor based on spiking neuron models,” Proceedings of the 2006 International Symposium on Nonlinear Theory and its Applications (WIP session), pp. 84-88, Bologna, Italy (Sep. 11-14, 2006).
130. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A watchdog sensor for assuring the quality of various perishables with subthreshold CMOS circuits,” Proceedings of the 2006 Symposia on VLSI Technology and Circuits, pp. 194-195, Honolulu, USA (Jun. 13-17, 2006).
131. A.K. Kikombo, T. Hirose, T. Asai, Y. Amemiya, “Non-linear dynamical systems consisting of single-electron oscillators,” Proceedings of the 14th International Workshop on Nonlinear Dynamics of Electronic Systems, pp. 81-84, Dijon, France (Jun. 6-9, 2006).
132. A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, “A neuromorphic LSI performing noise-shaping pulse-density modulation with ultralow-power subthreshold neuron circuits,” Proceedings of the 10th International Conference on Cognitive and Neural Systems, p. 53, Boston, USA (May 17-20, 2006).
133. G.M. Tovar, T. Hirose, T. Asai, and Y. Amemiya, “Precisely-timed synchronization among spiking neural circuits on analog VLSIs,” Proceedings of the 2006 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 62-65, Honolulu, USA (Mar. 3-5, 2006).
134. T. Hirose, T. Matsuoka, K. Taniguchi, T. Asai, and Y. Amemiya, “Ultralow-power temperature-insensitive current reference circuit,” Technical Program and Abstracts of the 4th IEEE Conference on Sensors, p. 186, California, USA (Oct. 31-Nov.3, 2005).
135. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A CMOS watch-dog sensor for guaranteeing the quality of perishables,” Technical Program and Abstracts of the 4th IEEE Conference on Sensors, p. 186, California, USA (Oct. 31-Nov.3, 2005).
136. T. Hirose, T. Asai, and Y. Amemiya, “Spiking neuron devices consisting of single-flux-quantum circuits,” Program and Abstracts of the 18th International Symposium on Superconductivity, p. 327, Tsukuba, Japan (Oct. 24-26, 2005).
137. T. Hirose, K. Ueno, T. Asai, and Y. Amemiya, “Single-flux-quantum circuits for spiking neuron devices,” Proceedings of the 2nd International Conference of Brain-inspired Information Technology, p. 67, Kita-kyushu, Japan (Oct. 7-9, 2005).
138. K. Nakada, T. Asai, T. Hirose, and Y. Amemiya, “Analog current-mode implementation of central pattern generator for robot locomotion,” Proceedings of the International Joint Conference on Neural Networks 2005, pp. 639-644, Montreal, Canada (Jul. 31-Aug. 4, 2005).
139. K. Nakada, T. Asai, T. Hirose, and Y. Amemiya, “Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1923-1926, Kobe, Japan (May 23-26, 2005).
140. T. Oya, T. Asai, R. Kagaya, T. Hirose, and Y. Amemiya, “Depressing properties of a hardware synapse on a single-layer nanodot array,” Proceedings of the 2005 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 159-162, Hawaii, USA (Mar. 4-6, 2005).
141. T. Oya, T. Asai, R. Kagaya, T. Hirose, and Y. Amemiya, “Application of the competitive neural-network architecture to single-electron circuit systems,” Proceedings of the 2005 RCIQE International Seminar for 21st Century COE Program: Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III), pp. 148-149, Sapporo, Japan (Feb. 8-10, 2005).
142. T. Oya, T. Asai, R. Kagaya, T. Hirose, and Y. Amemiya, “Neuromorphic single-electron circuit and its application to temporal-domain neural competition,” Proceedings of the 2004 International Symposium on Nonlinear Theory and its Application, pp. 235-239, Fukuoka, Japan (Nov. 29-Dec. 3, 2004).
143. M. Takahashi, T. Oya, T. Hirose, T. Asai, and Y. Amemiya, “A CMOS reaction-diffusion device using minority-carrier diffusion in semiconductors,” Proceedings of the 2004 International Symposium on Nonlinear Theory and its Application, pp. 601-605, Fukuoka, Japan (Nov. 29-Dec. 3, 2004).
144. K. Nakada, T. Asai, T. Hirose, and Y. Amemiya, “Digital VLSI implementation of ultra-discrete Burgers cellular automata for simulating traffic flow,” Proceedings of the IEEE International Symposium on Communications and Information Technologies 2004, pp. 394-397, Sapporo, Japan, (Oct. 26-29, 2004).
145. T. Hirose, Yoshimura R., Ido T., T. Matsuoka, and Taniguchi K., “Watchdog circuit for product degradation monitor using subthreshold MOS current,” Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, pp. 150-151, Tokyo, Japan (Sep. 15-17, 2004).
146. T. Oya, T. Asai, R. Kagaya, T. Hirose and Y. Amemiya, “A competitive neural network with neuromorphic single-electron circuits,” Proceedings of the 5th International Conference on Biological Physics, B09-342, Gothenburg, Sweden (Aug. 23-27, 2004).
147. Ikebe M., T. Asai, T. Hirose, and Y. Amemiya, “A quadrilateral-object composer for binary images with reaction-diffusion cellular automata,” Proceedings of the 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 406-409, Fukuoka, Japan (Aug. 4-6, 2004).
148. T. Asai, Kanazawa Y., T. Hirose, and Y. Amemiya, “A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection,” Proceedings of the 2004 International Joint Conference on Neural Networks, W107, Budapest, Hungary (Jul. 25-29, 2004).
149. M. Furuhashi, T. Hirose, H. Tsuji, M. Tachi, and K. Taniguchi, “Boron segregation model at Si(100)/SiO2 interface,” Proceedings of the 10th International Conference on Defects-Recognition, Imaging and Physics in Semiconductors, p.18, Batz surmer, France (Sep. 29-Oct.2, 2003).
150. H. Tsuji, R. Kim, T. Hirose, M. Furuhashi, M. Tachi, and K. Taniguchi, “Photoluminescence study on evolution of {311} defects in self-implanted silicon during low temperature annealing,” Proceedings of the 2003 International Meeting for Future Electron Devices, Kansai, Japan (Jul. 15-16, 2003).
151. H. Tsuji, R. Kim, T. Hirose, M. Furuhashi, M. Tachi, and K. Taniguchi, “Photoluminescence and ab initio study of {311} defect nucleation in Si,” Proceedings of the 3rd International Workshop on Junction Technology, Tokyo, Japan (Dec. 2-3, 2002).
152. Shano T., R. Kim, T. Hirose, Y. Furuta, H. Tsuji, M. Furuhashi, and K. Taniguchi, “Realization of ultra-shallow junction: Suppressed boron diffusion and activation by optimization fluorine co-implantation,” Proceedings of the 2001 International Electron Devices Meeting, pp. 37.4.1-4, Washington, D.C., USA (Dec. 3-5, 2001).
153. H. Tsuji, R. Kim, T. Hirose, Shano T., Y. Kamakura, and K. Taniguchi, “Photoluminescence study of {311} defect-precursors in self-implanted silicon,” Proceedings of the 9th International Conference on Defects-Recognition, Imaging and Physics in Semiconductors, p. 28, Rimini, Italy (Sep. 24-28, 2001).
154. T. Hirose, Shano T., R. Kim, H. Tsuji, Y. Kamakura, and K. Taniguchi, “Atomic configuration study of implanted F in Si based on experimental evidence and ab initio calculations,” Proceedings of the 9th International Conference on Defects-Recognition, Imaging and Physics in Semiconductors, p. 57, Rimini, Italy (Sep. 24-28, 2001).
155. K. Deguchi, S. Uno, A. Ishida, T. Hirose, Y. Kamakura, and K. Taniguchi, “Degradation of ultra-thin gate oxides accompanied by hole direct tunneling: can we keep long-term reliability of p-MOSFETs?,” Proceedings of the 2000 International Electron Devices Meeting, pp. 327-330, San Francisco, USA (Dec. 11-13, 2000).
156. R. Kim, Aoki T., T. Hirose, Y. Furuta, S. Hayashi, T. Shano, and K. Taniguchi, “Modeling of arsenic transient enhanced diffusion and background boron segregation in low-energy As+ implanted Si,” Proceedings of the 2000 International Electron Devices Meeting, pp. 523-526, San Francisco, USA (Dec. 11-13, 2000).